1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to electrostatic discharge protection devices therefor.
2. Description of Related Art
For Lightly Doped Drain (LDD) technology Input/Output Electrostatic Discharge (ESD) protection suffers from the LDD structures. While the conventional Source/Drain structure has the advantage of providing improved ESD protection, it has the disadvantage that to achieve that advantage, the burden of providing one extra masking step is required to secure the desired protection. The disadvantages of increased cost and increased cycle time are significant. The conventional Source/Drain structure requires that extra masking step burdening the manufacturer with increased process cycle time and the resultant increased processing costs.
U.S. Pat. No. 5,142,345 of Miyata for "Structure of Input Protection Transistor in Semiconductor Device Including Memory Transistor Having Double-Layered Gate and Method of Manufacturing Semiconductor Device Including Such Input Protecting Transistor" uses an EPROM device as an input protection device. Referring to FIGS. 5 and 6 of Miyata, an input protection transistor 180 is provided. The gate is composed of a laminated polysilicon 1/dielectric/polysilicon 2 (212/214/216) structure and the ESD N+ S/D formation (source/drain regions 206a and 206b) formed before the normal LDD device as explained in detail in FIG. 9A-9K of Miyata et al. The input protection transistor is formed in region 36 in FIGS. 9A-9E. The LDD device is formed in region 35 is formed starting with FIG. 9E.
Additionally, U.S. Pat. Nos. 4,937,639 of Yao et al, 4,952,994 of Lin, 5,027,252 of Yamamura, 5,225,702 of Chatterjee, and 5,229,635 show ESD protection devices and methods of making devices.